When AI outruns the microchip: imec’s bold acceleration plan

The future is speeding up, and microchips are struggling to keep pace.

Generative artificial intelligence, from ChatGPT and multimodal assistants to emerging agentic systems, has rapidly shifted from a research curiosity to a ubiquitous force reshaping business, science, and society. But hidden beneath the headlines lies a brewing tension: while AI evolves by the month, the semiconductor world moves in years. This growing gap between AI ambition and chip reality is the defining challenge of our time, one that imec, Europe’s premier nano-electronics research center, is racing to solve.

“A new era of grand chip scaling challenges has begun,” says CEO Luc Van den Hove in imec's outlook for 2026; not as a warning, but as a call to arms.

Why today’s chip roadmap isn’t enough

For decades, chipmakers rode the cadence of Moore’s Law — the idea that transistor density would double roughly every two years, delivering ever-greater performance at lower cost. But that rhythm, once the backbone of technological progress, has slowed. At the same time, AI workloads are exploding in size and complexity, demanding more compute power, higher energy efficiency, and better integration across systems.

“The pace at which AI has permeated virtually every aspect of society has been nothing short of mind-blowing,” says Van den Hove, and therein lies the tension. The semiconductor design-to-manufacturing cycle is measured in years, while AI advances can shift direction in months or even weeks.

Imec’s challenge and opportunity is to align chip innovation with AI’s runaway pace. This means moving beyond incremental tweaks on existing designs and embracing transformative approaches that rethink the entire computing stack.

Cross-technology co-optimization: A new strategy

At the heart of imec’s 2026 vision is a concept called cross-technology co-optimization (XTCO), described by CEO-elect Patrick Vandenameele as “a disruptive, holistic approach to scaling.”

In today’s systems, compute engines, memory modules, power delivery, thermal management, and reliability are often developed independently. XTCO flips that model: it insists that all these components must be co-designed: optimized together, rather than in isolation.

“Next-generation AI systems are becoming increasingly complex… to meet their demanding memory, power, thermal, and reliability requirements, chips are evolving into heterogeneous assemblies,” Vandenameele explains.

In practice, this means rethinking everything from how transistors are arranged on a wafer to how multiple chips communicate within a single server. The goal? Systems that are not just faster, but also more energy-efficient and adaptable to changing AI workloads.

Beyond silicon: High-NA EUV and photonics

Yet XTCO is just one piece of the puzzle. To push chip architecture into the next frontier, imec continues to invest in advanced fabrication techniques and complementary technologies.

A central focus is High-NA EUV lithography, the next leap in patterning that enables features smaller than 2 nm. At imec and ASML’s joint High-NA EUV Lithography Lab in Veldhoven, researchers are already refining this toolset, working with partners to ensure it can reliably pattern tomorrow’s logic and memory structures.

But raw compute isn’t enough. For massive AI systems, especially those in cloud data centers, photonics is emerging as a critical technology. By using light instead of electrons to shuttle data, photonic interconnects promise ultra-fast, low-energy links between chips and across racks, easing one of the biggest bottlenecks in high-performance AI.

From lab to market: Bringing breakthroughs to scale

Technical breakthroughs alone don’t change the world. Imec recognizes that the real impact comes when innovations make it into products and services.

To that end, the organization is doubling down on venture acceleration, IP expansion, and early access to advanced semiconductor platforms. Through initiatives like the EU Chips Act-supported NanoIC pilot line, fabless companies can experiment with cutting-edge nodes well before commercial volume production.

IC-Link, imec’s ASIC support service, plays a crucial role here as well, bridging the gap between lab-born innovation and manufacturable solutions.

A future defined by agility

If there’s a central theme in imec’s 2026 strategy, it’s agility. In an era where AI paradigms can shift faster than chip cycles, the old script no longer works. Building programmable, modular hardware that adapts to new software demands, rather than chasing each new algorithm with a bespoke chip, may be one answer. Industry voices, including imec leadership, have flagged this shift as essential to avoid obsolete silicon and stranded R&D investments.

As AI moves into agentic and physical realms (where systems learn, act, and adapt in the real world), the need for flexible, energy-efficient computing will only intensify.

The imec bet: Lead the change, don’t follow it

In the end, imec’s vision is ambitious not just because of the technologies it champions, but because of the mindset it embodies: to lead the change rather than adapt to it. In a world where microchips can no longer be scaled one transistor at a time, imec aims to scale innovation itself: across technologies, industries, and use cases.

“For 2026 and beyond, we aren’t just optimizing chips. We’re reimagining what computing can be,” says Van den Hove.