The future of computing will not be solved by a faster chip

A bee is a hard act to follow.

It can navigate a chaotic environment, recognise patterns, react instantly to movement and make decisions while flying — all on an exceptionally lean energy budget. Compared with that, today’s drones are still rather cumbersome machines: capable, certainly, but nowhere near as intelligent or efficient as the tiny biological systems they try to emulate.

For Paul Detterer, an R&D design engineer at imec’s Hardware and Efficient AI group at Holst Centre, that contrast is more than a nice metaphor. It is a design brief for the future of computing.

As conventional chip scaling approaches its limits, the next gains cannot come only from making transistors smaller or processors faster. The pressure is increasingly on energy and bandwidth: how much data must travel, how often it travels, and how much electricity is consumed simply shuttling information back and forth between memory and processing units.

That is where biology offers a different model.

Biological neurons do not constantly exchange vast streams of data. They communicate through sparse, event-driven signals — spikes — and respond when something actually happens. Memory is distributed rather than located in a single separate block. And there is no central clock synchronising every action. Yet the system remains remarkably responsive, even though signals in biological neurons move far more slowly than those in silicon.

“It seems to be event-driven,” Detterer said. “The system only reacts if there is something happening out there.”

That principle matters especially at the edge: in wearables, smart cameras, robots, drones and autonomous vehicles. These systems cannot always send their data to a distant data centre, wait for an answer and then act. They need to process information locally, in real time, and within a limited power envelope.

From brain-inspired chips to useful AI

imec has spent years exploring this territory through neuromorphic computing: hardware that takes inspiration from the way biological neural systems operate. The research starts with algorithms and models, but stretches all the way down to chip architecture and silicon implementation.

The team has already produced several tape-outs, including a new second-generation chip that has recently returned from the fab and is now being measured. Early devices were closely modelled on spiking neural networks, where artificial neurons communicate through discrete events rather than continuous signals.

That delivered impressive efficiency. But Detterer also acknowledged a familiar problem in deep-tech development: a technically elegant solution is not automatically a broadly useful one.

The first chips were highly efficient, but their applications were limited. The next step, therefore, was not to abandon neuromorphic principles, but to combine them with more general forms of AI.

The result is a heterogeneous architecture: some parts of the chip are flexible enough to run different algorithms and models, while others are more specialised and hardwired for efficiency. It is an attempt to navigate one of the defining trade-offs in AI hardware.

Flexibility costs energy. Efficiency can cost flexibility. The real challenge is not choosing one over the other, but deciding where each belongs.

The real bottleneck is data movement

That trade-off becomes even sharper in the debate around in-memory computing. In conventional computing systems, data is frequently moved between memory and the processor. That movement consumes energy and creates delays. In-memory computing promises to reduce that overhead by carrying out calculations much closer to (or inside) the memory itself.

But there is a catch. imec had already explored in-memory computing years ago, Detterer said. The resulting technology was highly efficient, but designed around one particular application. It could not easily be repurposed. The team therefore shifted towards near-memory computing: still more efficient than conventional architectures, but more flexible and scalable.

Now the question is open again. How far should computing move into memory? Where does specialisation create genuine advantage, and where does it become a constraint?

“That is the balance we are trying to find,” Detterer said: between near-memory and in-memory computing, between low power and high performance, and between a chip optimised for one task and a platform that can evolve as AI applications evolve.

It is a question with consequences well beyond a single processor. The demand for AI is accelerating, but the industry cannot afford development cycles in which algorithms, models, software and hardware are designed one after another, each waiting for the previous layer to be completed.

Detterer described the traditional route as a long sequence: from algorithm to AI model, from training to software mapping, from hardware design to final application. The future, he argued, requires those layers to be developed much more in parallel.

That makes co-design essential. Hardware engineers need to understand what models will run on their chips. Algorithm designers need to know what hardware trade-offs are possible. And AI itself may increasingly help explore design options earlier in the process, shortening the route from an initial concept to working silicon.

A central question for Watt Matters in AI

Detterer’s presentation was not simply about a new chip. It was about a deeper shift in how the AI world defines progress.

For years, progress meant more compute, larger models and greater scale. The next phase will demand a more difficult question: what computation is really necessary, where should it happen, and how can it be delivered without turning energy consumption into the limiting factor?

That is also the central question behind Watt Matters in AI, the IO+ conference on energy-efficient artificial intelligence. Taking place on 16 and 17 November at the High Tech Campus Eindhoven, the event brings together the hardware, software, systems and policy perspectives needed to move beyond incremental efficiency gains. Neuromorphic computing, memory-centric architectures and edge AI are exactly the kinds of technologies that will be part of that conversation.

The bee, in that sense, is not the answer. But it remains a useful provocation. Nature has already shown that intelligence does not necessarily require immense power. The task for Europe’s chip and AI ecosystem is to learn which principles can be translated into silicon — and to do so fast enough for the applications that are already arriving.