Inside the imec-ASML alliance: How to keep Moore’s Law moving

For 35 years, imec and ASML have advanced lithography in lockstep. As imec expands its Leuven pilot line with High-NA EUV under the European Chips Act, the partnership becomes the hinge for Europe’s chip ambitions - and for AI efficiency.

When Luc Van den hove talks about imec’s roadmap, ASML is never more than a sentence away. “We’ve been working for the last 35 years very closely with ASML to each time introduce more performant lithography techniques in order to enable two-dimensional scaling,” the outgoing CEO said. In a world where AI’s compute appetite threatens to outpace the planet’s power budget, that collaboration is the point of the spear: make vastly more capable chips per watt by perfecting the light that writes them.

A feedback loop that spans decades

Imec’s model is unusual among public research organizations: a neutral, shared pilot line where rival players co-develop the future under one roof. Lithography is the central rhythm section, and ASML is the drummer. Van den hove described a tight technical cadence: imec pathfinds devices and process modules; ASML brings step-function advances in lithography; together they close the loop with the ecosystem - photoresist makers, etch and deposition suppliers, foundries, and fabless designers - so the next generation is manufacturable. “We bring together the entire ecosystem… in particular also ASML,” he said.

That loop is how chipmaking continues to shrink features while maintaining yields and energy efficiency. It’s also why imec calls lithography the non-negotiable enabler of everything else on the roadmap, from new transistor architectures to 3D stacking.

High-NA EUV: installing the next gear

The next leap is literal hardware: High-NA EUV. Imec’s Fab3 already runs what Van den hove fairly called “the world’s most advanced R&D pilot line.” The expansion plan - €2.5 billion in new tools and 6,000 m² of additional cleanroom - adds Fab4, physically linked and automated with Fab3, and equips it with “the full suite of next-generation ASML tools like the High-NA EUV machine.” Construction is slated to start next year; the combined Fab3-Fab4 line is targeted to be ready by the end of 2028.

Luc van den hove, imec

Why this matters: High-NA tightens focus, enabling finer features and better process windows. In practice, it’s the cornerstone for the next eight to ten nodes on imec’s scaling roadmap, and the foundation for the energy savings AI demands. “Many people have been saying Moore’s law is dead,” Van den hove said. “There is this phenomenal demand… and that creates this enormous push to extend Moore’s law.”

Energy is the new performance: litho at the center

Imec casts the challenge in blunt terms: AI’s compute curve is exponential; if technology doesn’t deliver far higher performance per watt, energy use will explode. Lithography is where the baton passes from physics to systems. High-NA EUV underwrites denser, lower-capacitance devices and shorter interconnects, which in turn lower dynamic power. And when 2D scaling slows, litho still sets the stage for 3D: stacking N- and P-devices, fusing memory over logic, and stitching chiplets with ultra-short links: steps imec bundles under “CMOS 2.0.”

Critically, imec and ASML don’t do this alone. Each lithography advance requires co-innovation with resists, etch, deposition, and metrology to ensure the entire flow is printable, inspectable, and yieldable. The pilot line is where those pieces come together and mature.

Europe’s sovereignty, stated in one sentence

Pressed on digital sovereignty, Van den hove didn’t reach for slogans. He pointed out strengths. “You cannot make any chip in the world without ASML technology and imec processes,” he said. The remark lands harder in context: Europe may not fabricate most leading-edge chips, but it owns the critical choke points that make those chips possible. The European Chips Act’s decision to back imec’s expansion with its largest project award reflects that reality and bets on the imec-ASML axis to grow Europe’s share of the value chain.

For Van den hove, sovereignty also means design capability on the leading edge, because chips designed in Europe generate the demand that justifies local capacity. Here again, lithography matters: you can’t co-optimize systems and processes if you don’t understand (and have hands-on access to) the litho realities. Imec’s IC-Link and venturing programs make that access concrete for startups and scale-ups, feeding a pipeline of European fabless players who design with the process, not despite it.

A neutral ground where competitors collaborate

There’s a paradox at the heart of imec’s model: the more competitive the industry becomes, the more it needs a trusted, neutral place to co-develop pre-competitive technologies. That calls for a culture built on integrity, where confidentiality holds even when arch-rivals share a hallway, and connectedness, pulling materials, equipment, foundries, hyperscalers, and system OEMs into a single conversation. ASML’s presence in that room isn’t symbolic; it’s the practical way the industry derisks the next lithography node before billions are committed.

Continuity of the alliance

Leadership transitions can unsettle partnerships. Imec’s plan is the opposite: continuity by design. Van den hove becomes Chairman on April 1, 2026, staying close to global stakeholder management; Patrick Vandenameele, a physicist-turned-entrepreneur who later built imec’s venturing and then strategy, becomes CEO. “Don’t expect me to change everything,” Vandenameele said. The strategy - extend scaling with ASML’s High-NA EUV, fuse it with 3D integration and photonic interconnects, and open the pilot line to the next generation of European designers - stands.

In Leuven, the light source sits in Veldhoven. The partnership is the bridge. And for the next decade of AI-era chips, the imec-ASML handshake looks set to remain Europe’s most consequential R&D alliance.