ASML's tiny skyscraper maker

Semiconductors are running out of room. Despite the ever-shrinking size of transistors, demand is outpacing the number of devices you can pack onto a single die. Making chips larger introduces its own problems with manufacturing yield, so the only way is up. That’s essentially what engineers are doing inside today’s most advanced processors. Welcome to the world of 3D chip packaging, where tiny silicon skyscrapers are reshaping everything from AI to gaming.

And now, ASML has introduced a new lithography system designed to make stacking and packaging chips even more efficient: the ASML Twinscan XT:260. It’s a technological marvel quietly influencing how the next generation of smart devices comes to life.

Why Stack Chips?

For decades, we made computers faster by cramming more transistors onto flat silicon wafers—the classic “Moore’s Law” promise. But physics has caught up. Squeezing in more circuitry on a single layer is getting harder, hotter, and way more expensive.

Enter 3D chip packaging, an elegant workaround: if you can’t go wider, go taller.

Think of it like upgrading from a sprawling suburban neighborhood to a sleek downtown high-rise. Instead of spreading components out, engineers now stack them—layer upon layer—like floors in a building. Each floor could be a processor, a memory unit, or even specialized AI hardware—all connected by lightning-fast elevators known as through-silicon vias (TSVs).

This isn’t just cool engineering—it’s essential. Modern applications like generative AI, self-driving cars, and cloud computing demand insane amounts of data movement. And nothing moves data faster than keeping it close. In 3D stacks, signals travel mere microns instead of millimeters, slashing delays and saving power.

Leading tech giants aren't waiting around. Intel's Foveros, TSMC's CoWoS, and System-on-Integrated-Chips (SoIC) are already turning sci-fi dreams into shipping products. Apple’s M-series chips? NVIDIA’s AI behemoths? AMD’s Zen architecture? All powered by some form of advanced packaging technologies that rely on precise 3D integration.

But stacking chips isn’t easy. Imagine trying to perfectly align two sheets of paper covered in microscopic wiring, with zero mistakes, even if one sheet is slightly bent. Now do it millions of times per second, across hundreds of wafers. That’s where the real magic begins.

The XT:260 aligning everything

This is where the ASML Twinscan XT:260 comes in, a state-of-the-art lithographysystem designed specifically for wafer-level processes involved in advanced packaging.

The XT:260 uses older-style i-line light—but supercharged. It exposes a surface area four times larger than previous tools in a single shot. This gives up to four times higher productivity. While old systems struggled to keep pace, the XT:260 churns through over 200 wafers per hour, helping meet booming demand driven by AI and data centers. But it's speciality lies in alignment.

One of the biggest headaches in stacking chips is overlay error; when layers don’t line up perfectly. Even a tiny misalignment means broken connections and dead chips. Previous tools aligned wafers first, then exposed them. But warping, heat, and vibration could throw things off.

The XT:260 changes the game: it aligns while exposing. Think of it like drawing a perfect circle on a spinning record—not after it starts moving, but as it spins. This real-time correction slashes cumulative errors, boosting yields and lowering costs.

Stacked chips often involve thick, uneven, or slightly warped wafers. Remember, this is all on the nanoscale, so the perfectly smooth wafer you see with the naked eye might not be that smooth. After being baked, bonded, and cooled multiple times, imperfections arise. Many older machines choke on such imperfections. The XT:260 is engineered to handle messy reality, ensuring consistent quality no matter how twisted the wafer gets.

Powering the Rise of High-Bandwidth Memory (HBM)

If AI were a car, high-bandwidth memory (HBM) would be its nitro boost. Used in everything from ChatGPT servers to PlayStation 5 graphics cards, HBM relies on tightly stacked DRAM chips linked through ultra-dense interconnects.

The XT:260 enables critical steps in creating these stacks—including patterning redistribution layers (RDLs) and preparing surfaces for hybrid bonding, where copper atoms literally fuse across dies at room temperature. Without near-perfect alignment and repeatability, hybrid bonding fails.

Experts predict the global semiconductor market will surpass $1 trillion by 2030, fueled largely by AI and high-performance computing. At the center of this explosion isn’t just raw processing power; it’s integration. Being able to combine best-in-class pieces - CPUs, GPUs, memory, and custom AI accelerators - and glue them together seamlessly using advanced packaging technologies gives companies unmatched flexibility.

“The AI era doesn’t just need smaller transistors,” says industry analysts familiar with ASML’s roadmap. “It needs smarter ways to connect them.” The smart connection is what the XT:260 is about.