AI’s energy wall - and imec’s plan to break through

At a Leuven briefing on September 30, 2025, imec’s leadership warned that AI’s hunger for compute is on a collision course with planetary limits. Their answer: squeeze far more performance per watt by pushing Moore’s Law, going 3D, and lighting up chips with photonics.

AI isn’t just a software story; it’s an energy story. That was Luc Van den hove’s central message as he outlined why imec is retooling its pilot line and roadmap around efficiency. “Over the recent years, artificial intelligence has seen an enormous exponential increase in required compute power,” he said. “If we don’t develop new and more performing technology, this would result in an exponential increase in energy consumption, which clearly is not sustainable.”

Imec’s response starts where it always has: keep scaling. “Many people have been saying Moore’s law is dead,” Van den hove noted. “There is this phenomenal demand for more advanced technologies… and that creates this enormous push to extend Moore’s law.” High-NA EUV with ASML sits at the center of that push, alongside new transistor architectures that keep two-dimensional (2D) scaling alive, even if progress slows.

CMOS 2.0

But imec’s energy playbook isn’t just thinner lines; it’s a third dimension. First, stack transistors to increase density without the power costs associated with ever-shrinking geometry. Second, stack chips, especially memory on logic, so data doesn’t waste energy shuttling off-chip. Third, stitch chiplets together with advanced packaging to build “compute systems with close to a trillion transistors” yet shorter, more efficient data paths. Imec brands this blended approach CMOS 2.0: 2D scaling + 3D integration + new device concepts, all aimed at performance per watt.

Luc van den hove, imec

Photonics

There’s a crucial missing piece in most AI systems today: the links between those chiplets. Copper traces don’t scale gracefully. Imec’s answer is photonics: moving from “pluggable optics” to chip-package optics, and ultimately photonic interposers with waveguides as light-speed highways between dies. The goal is brutal: slash interconnect power without throttling bandwidth.

If the roadmap is the “what,” Leuven’s expansion is the “how.” Backed by the European Chips Act, imec will invest €2.5 billion in tools and 6,000 m² of cleanroom space to stay ahead of the curve, installing High-NA EUV and building Fab4 (integrated with today’s Fab3) to prototype these energy-saving architectures at scale. “We are committed to making sure that this infrastructure remains the most advanced R&D pilot line on the planet,” Van den Hove said.

Not optional

Why the urgency? Because efficiency isn’t optional for AI’s next wave, in cars, in clinics, and in the cloud. More models and more parameters without radically better joules-per-operation means, ultimately, less AI or more emissions. Imec’s bet is that system-technology co-optimization - device, packaging, memory hierarchy, and photonic I/O designed as one - can bend the curve.

“Exponential compute cannot come with exponential energy,” Van den hove argued. With CMOS 2.0 and photonics in the loop, imec wants to prove it doesn’t have to.

Watt Matters in AI

Watt Matters in AI is a conference that aims to explore the potential of AI with significantly improved energy efficiency. In the run-up to the conference, IO+ publishes a series of articles that describe the current situation and potential solutions. Tickets to the conference can be found at wattmattersinai.eu.

View Watt Matters in AI