For many years, a bottleneck in technological development has been how to get processors and memories to work faster together. Now, researchers at Lund University in Sweden have presented a new solution integrating a memory cell with a processor, which enables much faster calculations, as they happen in the memory circuit itself.<\/p>\n\n\n\n
In an article in Nature Electronics<\/em>, the researchers present a new configuration, in which a memory cell is integrated with a vertical transistor selector, all at the nanoscale. This brings improvements in scalability, speed and energy efficiency compared with current mass storage solutions.<\/p>\n\n\n\n The fundamental issue is that anything requiring large amounts of data to be processed, such as AI and machine learning, requires speed and more capacity. For this to be successful, the memory and processor need to be as close to each other as possible. In addition, it must be possible to run the calculations in an energy-efficient manner, not least as current technology generates high temperatures with high loads, writes Lund University in a press release<\/a>.<\/p>\n\n\n\n The problem of processors\u2019 computations happening much faster than the speed of the memory unit has been well known for many years. In technical terms, this is known as the \u201fvon Neumann bottleneck\u201d. The bottleneck happens because the memory and computation units are separate, and it takes time to send information back and forth via what is known as a data bus, which limits speed.<\/p>\n\n\n\n \u201fProcessors have developed a lot over many years. On the memory side, storage capacity has steadily increased, but things have been pretty quiet on the function side\u201d, says Saketh Ram Mamidala, doctoral student in nanoelectronics at Lund University and one of the authors of the article.<\/p>\n\n\n\n Traditionally, the limitation has been in the construction of circuit boards with units placed next to each other on a flat surface. Now, the idea is to build vertically in a 3D configuration and to integrate the memory and processor, with computations taking place within the memory circuit itself.<\/p>\n\n\n\n \u201fOur version is a nanowire with a transistor at the bottom, and a very small memory element located further up on the same wire. This makes it into a compact integrated function where the transistor controls the memory element. The idea has been around before, but it has proven difficult to achieve performance. Now, however, we have shown that this can be achieved and that it works surprisingly well\u201d, says Lars-Erik Wernersson, professor of nanoelectronics.<\/p>\n\n\n\n The researchers are working with a RRAM (Resistive Random Access Memory) memory cell, which is nothing new in itself; what is new is how they have succeeded in achieving a functional integration that gives rise to great possibilities. It opens up potential new research fields and new, improved functions in everything from AI and machine learning to ordinary computers as well, eventually. Future applications could, for example, be various forms of machine learning such as radar-based gesture control, climate modelling or development of various drugs.<\/p>\n\n\n\n \u201fThe memory even works without a power supply\u201d, adds Saketh Ram Mamidala.<\/p>\n\n\n\n At Lund, researchers have long been successful when it comes to building nanowires in what is known as the III-V technology platform. The material integration in Lund is unique, and researchers have greatly benefited from the MAX IV laboratory in developing the material and being able to understand its chemical properties.<\/p>\n\n\n\n \u201fSolutions can probably be found in silicon as well, which is the most common material but, in our case, it is the choice of material that enables the performance. We want to pave the way for industry with our research\u201d, concludes Lars-Erik Wernersson.<\/p>\n\n\n\n Also interesting: <\/strong><\/em>Developing a quantum computer takes more than just money and people<\/a><\/p>\n","protected":false},"author":2084,"featured_media":345782,"template":"","meta":{"_acf_changed":false,"advgb_blocks_editor_width":"","advgb_blocks_columns_visual_guide":""},"categories":[8553],"tags":[29080,78995,30608,126426,53026,26403,77792],"location":[54353],"internal_archives":[],"class_list":["post-345772","selected","type-selected","status-publish","has-post-thumbnail","hentry","category-digital","tag-artificial-intelligence-en","tag-lund-university","tag-machine-learning","tag-nanoelectronics","tag-silicon","tag-supercomputer","tag-transistor","location-sweden"],"blocksy_meta":[],"acf":[],"featured_img":"https:\/\/ioplus.nl\/archive\/wp-content\/uploads\/2022\/01\/Ax4a0ynn-Chip2_0-1.jpg","coauthors":[],"author_meta":{"author_link":"https:\/\/ioplus.nl\/archive\/author\/mauro-mereu\/","display_name":"Mauro Mereu"},"relative_dates":{"created":"Posted 4 years ago","modified":"Updated 4 years ago"},"absolute_dates":{"created":"Posted on January 10, 2022","modified":"Updated on January 10, 2022"},"absolute_dates_time":{"created":"Posted on January 10, 2022 12:00 pm","modified":"Updated on January 10, 2022 12:00 pm"},"featured_img_caption":"\u00a9 Lund University","tax_additional":{"category":{"linked":["Digital<\/a>"],"unlinked":["Digital<\/span>"],"slug":"category","name":"Categories"},"post_tag":{"linked":["Artificial Intelligence<\/a>","Lund University<\/a>","machine learning<\/a>","nanoelectronics<\/a>","silicon<\/a>","Supercomputer<\/a>","transistor<\/a>"],"unlinked":["Artificial Intelligence<\/span>","Lund University<\/span>","machine learning<\/span>","nanoelectronics<\/span>","silicon<\/span>","Supercomputer<\/span>","transistor<\/span>"],"slug":"post_tag","name":"Tags"},"language":{"linked":["EN<\/a>"],"unlinked":["EN<\/span>"],"slug":"language","name":"Tags"},"post_translations":{"linked":["pll_61dc59a512f61<\/a>"],"unlinked":["pll_61dc59a512f61<\/span>"],"slug":"post_translations","name":""},"location":{"linked":["Sweden<\/a>"],"unlinked":["Sweden<\/span>"],"slug":"location","name":"Locations"},"internal_archives":{"linked":[],"unlinked":[],"slug":"internal_archives","name":"Internal Archives"}},"series_order":"","_links":{"self":[{"href":"https:\/\/ioplus.nl\/archive\/wp-json\/wp\/v2\/selected\/345772","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ioplus.nl\/archive\/wp-json\/wp\/v2\/selected"}],"about":[{"href":"https:\/\/ioplus.nl\/archive\/wp-json\/wp\/v2\/types\/selected"}],"author":[{"embeddable":true,"href":"https:\/\/ioplus.nl\/archive\/wp-json\/wp\/v2\/users\/2084"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/ioplus.nl\/archive\/wp-json\/wp\/v2\/media\/345782"}],"wp:attachment":[{"href":"https:\/\/ioplus.nl\/archive\/wp-json\/wp\/v2\/media?parent=345772"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ioplus.nl\/archive\/wp-json\/wp\/v2\/categories?post=345772"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ioplus.nl\/archive\/wp-json\/wp\/v2\/tags?post=345772"},{"taxonomy":"location","embeddable":true,"href":"https:\/\/ioplus.nl\/archive\/wp-json\/wp\/v2\/location?post=345772"},{"taxonomy":"internal_archives","embeddable":true,"href":"https:\/\/ioplus.nl\/archive\/wp-json\/wp\/v2\/internal_archives?post=345772"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}Solving the von Neumann bottleneck <\/h3>\n\n\n\n
The solution<\/h3>\n\n\n\n
Lund success in nanowires <\/h3>\n\n\n\n